In a semiconductor device tester, an interleaving method is adopted to realize a high-speed clock generator. In a typical interleave method, a plurality of clock signals, for example, n clock signals, are multiplied to generate a combined clock signal which is n times faster than each clock signal. The high-speed clock generator is usually used as a waveform formatter circuit in a driver and a comparator in a semiconductor tester. The driver supplies a test signal to a device under tested and has a waveform formatter unit therein. The comparator compares the resultant signal from the device under test with an expected signal.
The use of the waveform formatter circuit incorporating a high-speed clock generator increases because of the increase in the number of pins of a device to be tested. For instance, hundreds of pins are used in a recent semiconductor device. The necessity of the interleaving method also increases because of the increase in operating speed of such a device under test (DUT). Therefore, the circuit scale of the high-speed clock generator tends to increase.
An example of circuit configuration of the conventional waveform formatter for a tester driver is shown in FIG. 2. First of all, a reference clock is generated by a test rate generator 1. By using the reference clock, a 2-way interleaving unit 2 generates timing data (a) for a odd cycle, a clock (b) for the odd cycle, timing data (c) for an even cycle, and a clock (d) for the even cycle.
Next, a clock signal CLOCK1 is generated in a clock generator 11 as follows: A timing data memory 111 sets the delay data to a counter type delay element 112. This counter type delay element 112 begins counting when the specified clock (b) is applied from the 2-way interleaving unit. The counter type delay element 112 generates a carry over when the count value reaches the set value. As a result, an AND gate 113 opens and the reference clock REF.CLK is output from the AND gate 113. A delay element 114 delays a signal passing therethrough for the amount of delay time smaller than one signal period of the reference clock. The output of the delay element 114 is applied to an input terminal of an OR gate 119.
A timing data memory 115 sets the delay data to a counter type delay element 116. This counter type delay element 116 begins counting when the specific clock (d) is applied from the 2-way interleaving unit. The counter type delay element 116 generates a carry over when the count value reaches the set value. As a result, an AND gate 117 opens and the reference clock REF.CLK is output from the AND gate 117. Delay element 118 delays a signal passing therethrough for the amount of delay time smaller than one signal period of the reference clock). The output of the delay element 118 is applied to the other input terminal of the OR gate 119. Therefore, an odd cycle clock and an even cycle clock are ORed in the OR gate 119 which generates the combined clock signal CLOCK1.
Based on the same procedure as above, high-speed clocks CLOCK2, CLOCK3, and CLOCK4 are generated by clock generators 12, 13 and 14, respectively. Next, in a format control unit 3, these four clocks CLOCK1-CLOCK4 are used to format waveforms necessary for controlling the tester drivers. The output of the format control unit 3 is given to a RS flip-flop 4 and a RS flip-flop 5. In the RS flip-flop 4, the waveform of a driver 6 is generated with the set timing to a pin S and the reset timing to a pin R. In the RS flip-flop 5, the output control signal of the driver 6 is generated with the set timing to a pin S and reset timing to a pin R.
As mentioned above, using the 2-way interleaving method, the two clocks, the clocks (b) and (d) are interleaved together and generated as the high-speed clock CLOCK1. The high speed clocks CLOCK2-CLOCK4 are similarly generated by the clock generators. Thus, waveforms and control signals for the drivers are generated using these four clocks CLOCK1-CLOCK4.
FIG. 3 shows the timing chart of the clock generator of FIG. 2. The odd cycle clock (b) and the even cycle clock (d), and the odd cycle timing data (a) and the even cycle timing data (c) are provided as shown in FIGS. 3A-3D. The reference clock REF.CLK is shown in FIG. 3E. After the time TC1 from an edge of the odd cycle clock (b), the signal (FIG. 3F) from counter type delay element 112 opens the AND gate 113, and the reference clock REF.CLK is output (FIG. 3G). The reference clock REF.CLK is delayed by the time TD1 (FIG. 3H) in the delay element 114 and is applied to the OR gate 119. The total amount (TC1+TD1) of delay time in the output of the delay element 114 is a numerical value that corresponds to the odd cycle timing data (a).
After the time TC2 from an edge of the even cycle clock (d), the signal (FIG. 3I) from the counter type delay element 116 opens gate 117 so that the reference clock REF.CLK is output (FIG. 3J). The reference clock REF.CLK is delayed by the time TD2 (FIG. 3K) in the delay element 118 and is applied to the OR gate 119. The total amount (TC2+TD2) of delay time in the output of the delay element 118 is a numerical value that corresponds to the odd cycle timing data (c). The resulted odd cycle clock and the even cycle clock are ORed by the OR gate 119 to produce a combined clock signal which has a clock rate two times higher than the original clocks (FIG. 3L).
A prior art waveform formatter described above has the following problems.
In general, in a high speed semiconductor device, an I/O split scheme is used wherein each pin of the device separately contributes as an input pin or an output pin. In contrast, in a relatively lower speed semiconductor device, an I/O control scheme is used wherein a pin functions either as an input pin or an output pin under the control of the an I/O control signal. Therefore, for testing a low speed semiconductor device, a semiconductor device tester has to be provided with a driver control circuit. However, such a driver control circuit is useless in testing a high speed semiconductor device since the pin function is fixed.